Partcl

What do they actually do

Partcl builds GPU‑accelerated tools that speed up parts of the ASIC physical‑design flow so engineers can get timing and power feedback in seconds instead of hours. In a public beta/early access, they offer Boson (a static timing analysis engine) and Graviton (a timing‑aware placer) aimed at fast, iterative feedback after placement. The company publishes example runtimes (e.g., ~400 ms for ~100k gates, ~1 s for ~1M gates, ~3 s for ~7M gates) and claims large speedups versus legacy tools, with mature‑node signoff claims and advanced‑node support still maturing (Partcl).

Today’s workflow is: provide a netlist or intermediate database, run Boson/Graviton for quick timing/power estimates, identify hotspots, then iterate RTL or constraints to catch issues earlier in the cycle and reduce slow handoffs to PD teams (Partcl, YC profile). Access is via contact/beta sign‑up; the site highlights users like AI accelerator, embedded/IoT, and mobile SoC teams and mentions an academic tier (Partcl, FAQ, YC profile).

Who are their target customer(s)

• Chip architects and RTL designers building AI accelerators: They wait hours or days for timing/power feedback, so bugs surface late and iteration is slow, slowing performance tuning and schedule confidence.
• Physical‑design engineers on SoC teams: Heavyweight placement/timing runs create slow handoffs and late surprises that require time‑consuming fixes and reruns.
• SoC program managers and tapeout leads: Late discovery of timing or power issues drives slips and costly turnarounds, making tapeout dates hard to commit to.
• Small chip and AI‑SoC startups: Limited headcount and slow EDA runs constrain design‑space exploration, risking missed market windows.
• University research groups and academics: They need fast prototyping and lower‑cost access to tools; full commercial flows are too slow and expensive for many experiments.

How would they acquire their first 10, 50, and 100 customers

• First 10: Founder‑led, high‑touch pilots with YC portfolio companies and known PD leads: run the customer’s netlist for a week, deliver bespoke timing/power reports, and do a short integration to prove speed/accuracy and gather case studies (Partcl, YC profile).
• First 50: Convert pilots into paid, time‑boxed trials with clear success criteria; run targeted outbound to small chip teams and PD groups using initial case studies, and seed academic usage via the academic tier to build references (Partcl).
• First 100: Open a controlled self‑serve beta with upload templates, tutorials, and cloud‑hosted trial credits plus automated benchmarking dashboards; funnel trials into paid seats and pursue 1–2 hosting/integration partnerships to reduce friction for larger teams (Partcl).

What is the rough total addressable market

Top-down context:

Independent estimates put total EDA revenue in the low‑to‑mid tens of billions annually (e.g., ~$12.1B in 2023; other sources ~$15B in 2024) (Grand View Research, PSMarketResearch). IC physical design & verification is often ~35–40% of EDA spend, implying a multi‑billion‑dollar segment (Mordor Intelligence, Grand View Research).

Bottom-up calculation:

Near‑term: apply ~36% segment share to ~$12.1B 2023 EDA → roughly ~$4B physical‑design TAM for the categories Partcl addresses today. If they expand to a full RTL→GDSII flow, the addressable market broadens toward the full EDA total (low‑to‑mid tens of billions) (Grand View Research, PSMarketResearch).

Assumptions:

• Physical‑design share taken as ~36% of total EDA based on industry reports.
• Partcl’s current products map to timing, placement, and early power estimation inside the physical‑design segment.
• Sizing uses 2023–2024 reported market totals; methodology differences across firms create a range.

Who are some of their notable competitors

• Synopsys: Offers widely used sign‑off timing (PrimeTime) and digital implementation (Fusion Compiler/ICC2); strong at advanced node enablement and foundry certifications.
• Cadence: Provides Tempus (timing sign‑off) and Innovus (place & route) used across large SoC programs; deep integrations across RTL→GDSII.
• Siemens EDA (Mentor): Offers digital implementation (Aprisa) and sign‑off tools (e.g., Calibre) that complement or replace parts of physical‑design flows.
• Ansys: RedHawk‑SC and related tools focus on power integrity, EM/IR, and timing‑related sign‑off adjuncts in advanced nodes.
• OpenROAD Project: Open‑source RTL‑to‑GDS flow with placement, routing, and OpenSTA timing; used in academia and some startups for rapid iteration and research.}]}